This invention relates to a semiconductor transistor, and more particularly to a field effect transistor (FET) having a low parasitic resistance with a high breakdown voltage.
Recently, high-frequency and high speed FETs using compound semiconductors such as GaAs have actively been researched and developed for LSIs with a high speed performance and a low power consumption. The FET devices are required to have not only a high breakdown voltage property but also a low parasitic resistance. The breakdown voltage is an important factor for keeping a reliability in the device performance. A parasitic resistance in a parasitic region under a gate electrode of the FET is also a vary important factor for the device performances. A high parasitic resistance may impede the FET device and LSIs to have high frequency and high speed performances. It is, therefore, required to reduce a parasitic resistance as large as possible for obtaining ideal high speed and high frequency performance.
In the prior arts to reduce the parasitic resistance, the devices such as the FETs are fabricated by a selective ion-implantation method and an spitaxial growth method. The Japanese laid open patent application No. 62-230063 describes providing source and drain regions in the vicinity of a gate electrode for reducing parasitic resistances of source and drain region.
FIG. 1 is a cross sectional view illustrative of the above FET. This FET comprises a semi-insulated GaAs substrate 1, a channel layer 2 made of an undoped GaAs formed on the substrate 1, an electron supply layer 3 made of an n-type AlGaAs formed on the channel layer 2, a gate electrode 4 formed on the electron supply layer 3 and an electrode forming region 7 for source and drain electrodes 5 and 6.
The FET having the above structure may be fabricated by the following steps. Referring to FIG. 2A, the channel layer 2, the electron supply layer 3 and a p-type GaAs layer 8 are sequentially formed on the substrate 1. Referring to FIG. 2B, the gate electrode 4 is then formed on the p-type GaAs layer 8. Subsequently, the p-type GaAs layer 8 is selectively etched by using the gate electrode 4 as a mask to form a p-n type control electrode 8'. Referring to FIG. 2C, an insulating film 9 made of SiO.sub.2 is formed at opposite sidewalls of the etched p-type GaAs layer 8. The electron supply layer 3 is selectively etched by using the p-type GaAs layer 8 and the insulating film 9 used as masks. Referring to FIG. 2D, an n-type GaAs is grown at the etched portion by an spitaxial growth method to form the electrode forming region 7 for the source and the drain electrodes 5 and 6.
According to the foregoing prior arts, the electrode forming region 7 made of the n-type GaAs may be formed by the opposite sides of the gate electrode without any heat treatment to secure a high mobility of electrons confined in the channel layer so as to a two-dimensional electron gas (2DEG).
The prior art device would, however, be engaged with a disadvantage in a poor breakdown voltage and in a difficulty to reduce the parasitic resistance. In so far as the electron supply layer was formed to have the same length as that of the channel layer which is required to have the same length as the gate length of the gate electrode, it would be difficult to obtain both a high breakdown voltage and a possible reduction of parasitic resistance.